Many liquid crystal display apparatuses are used as display devices for computers, etc., and are expected to be widely used for TV in future years. However, a liquid crystal display panel in Twisted Nematic (TN) mode, which is now widely used, has some shortcomings, namely, narrow viewing angles and inadequate response speeds. Consequently, there are some major problems to be solved, for example, reduction in a contrast due to parallax or blurred outlines at the time of displaying moving images, in order to use the liquid crystal panel in TN mode for TV.
In recent years, research on OCB mode, which is replacing the above-described TN mode, has been conducted. The OCB mode of operation allows for wide viewing angles and enhanced response speeds, thereby being more suitable for displaying moving images than the TN mode.
FIG. 26 shows the structure of a commonly-used liquid crystal panel, which is common to the TN mode and the OCB mode. In FIG. 26, X1 to Xn indicate gate lines, and Y1 to Yn indicate source lines. Thin film transistors 2604 (hereinafter, referred to as a TFT) are provided as a switching element at intersection of the gate lines X1 to Xn with the source lines Y1 to Yn. The drain electrode of each TFT 2604 is connected to a pixel electrode of each pixel 2605 of the liquid crystal panel. In each pixel 2605, a liquid crystal is sandwiched between the pixel electrode and a counter electrode. A polarity of the counter electrode is controlled by a counter driving section 2603.
2602 indicates a gate driver for supplying a gate pulse, which controls the ON/OFF states of the TFTs 2604, to the gate lines X1 to Xn. The gate driver 2602 synchronizes with data supply to the source lines Y1 to Yn, and sequentially applies a potential to the gate lines X1 to Xn, which turns the states of the TFT 2604 ON. 2601 indicates a source driver for controlling a potential of the pixel electrode. A difference between a potential of the pixel electrode controlled by the source driver 2601 and a potential of the counter electrode controlled by the counter driving section 2603 is a voltage to be applied to the liquid crystal, and transmittance of each pixel 2605 is determined based on the above-described voltage.
Now, in a case where the liquid crystal panel in OCB mode is used, special processing, which is not performed for the TN mode, is required at the first stage of commencing image display. A state of OCB cells can be either a bend configuration or a splay configuration. In order to display an image on the liquid crystal panel in OCB mode, the OCB cells have to be in a bend configuration state. However, in general, the OCB cells are in a state of a splay configuration. Therefore, a state of the OCB cells has to be changed from a splay configuration to a bend configuration for displaying an image. Hereinafter, the above-described state change from a splay configuration to a bend configuration is referred to as a “transition”. In order to cause a transition of the OCB cells, special processing, for example, applying a high voltage for a predetermined period of time, is required. However, this processing is not directly related to the present invention, and therefore not further described herein.
After the above-described special processing causes the state of OCB cells to make a transition to a bend configuration, image display becomes possible. However, if a voltage equal to or greater than a predetermined level is not applied to the OCB cells for a period equal to or greater than a predetermined period of time, the state of the OCB cells returns back from a bend configuration to a splay configuration. Hereinafter, the above-described state change from a bend configuration to a splay configuration is referred to as a “back transition”. Thus, in order to continue image display using the liquid crystal panel in OCB mode, it is necessary to prevent a back transition. A back transition can be prevented by applying a high voltage to the OCB cells on a regular basis, as disclosed in Japanese Patent Laid-Open Publication No. H11-109921 and Japanese Liquid Crystal Society Journal, Apr. 25, 1999 (Vol. 3, No. 2) P.99 (17) through P.106 (24). Hereinafter, such a driving scheme of a liquid crystal panel, in which a high voltage is applied to the OCB cells on a regular basis, is referred to as “anti-back-transition driving”.
Now, as is well known, in a commonly-used liquid crystal panel typified by the OCB mode and the TN mode, a direct voltage applied to liquid crystal cells causes a problem such as burn-in. Therefore, when the liquid crystal panel is driven, it is necessary to perform so-called AC driving, in which polarity of the voltage applied to the liquid crystal cells is alternately inverted. This is also applied to a case where the liquid crystal panel is driven by the above-described anti-back-transition driving. However, in the above-described Japanese Patent Laid-Open Publication No. H11-109921 and Japanese Liquid Crystal Society Journal, a structure or an operation of a liquid crystal display apparatus in a case where an AC driving scheme is used for the anti-back-transition driving is not specifically described, and the above-described documents do not reveal a concrete method to apply an AC driving scheme to the anti-back-transition driving.
Now, the above-described documents disclose a scheme in which source drivers are placed on upper and under sides or a scheme in which driving frequency is doubled, in order to alternately write an image signal and a high voltage signal (a signal for periodically applying a high voltage to OCB cells). However, those schemes have a problem such as increase in cost because there is a need to use two source drivers, or inadequate writing of signal into OCB cells due to reduced signal writing time caused by the doubled driving frequency. Therefore, inventers of the present invention realize anti-back-transition driving by which increase in driving frequency is minimized. Hereinafter, as a related art of the present invention, a liquid crystal display apparatus to which anti-back-transition driving is applied will be described.
In FIG. 27, the structure of the above-described liquid crystal display apparatus according to the related art is shown. In FIG. 27, 2701 indicates a frequency converting section performing frequency conversion for an input video signal, 2702 indicates a driving pulse generating section generating pulses for controlling a source driver and a gate driver, respectively, 2601 indicates the source driver, 2602 indicates the gate driver, and 2703 indicates a liquid crystal panel in OCB mode. Note that, for the sake of convenience, the number of gate lines of the liquid crystal panel 2703 is assumed to be 12 lines, and one frame period is assumed to be composed of 12 horizontal scanning periods.
In this liquid crystal display apparatus, one image signal included in an input video signal and one non-image signal which is irrelevant to the input video signal are written into each pixel on the liquid crystal panel 2703 during one frame period. Here, the non-image signal is a signal for applying a high voltage to OCB cells in order to prevent a back transition. In order to realize the above-described writing, it is necessary to insert the non-image signal between the image signals composing the input video signal. Therefore, the frequency converting section 2701 of this liquid crystal display apparatus generates an output video signal by inserting one non-image signal for every four image signals (image signals corresponding to four lines) of an input video signal, and transfers it to the source driver 2601. At the same time, the frequency converting section 2701 also performs frequency conversion because mere insertion of the non-image signal could change a length of one frame period. That is, in order to transfer five signals including four image signals and one non-image signal to the source driver within a time period in which four image signals are input as an input video signal (that is, within four horizontal scanning periods), 1.25 times frequency conversion is performed.
In FIG. 28, a concrete structure of the frequency converting section 2701 is shown. A control signal generating section 2801 generates a writing clock, a reading clock, a read enable signal, an output switching control signal, and an output synchronizing signal, respectively, based on an input synchronizing signal. An input video signal is synchronized with the writing clock, and written into a line memory 2802. Then, the input video signal written into the line memory 2802 is synchronized with the reading clock whose frequency is 1.25 times higher than that of the writing clock, and read from the line memory 2802. Based on the output switching control signal, an output signal selecting section 2804 selects either an output of the line memory 2802 or an output of a non-image signal generating section 2803, and outputs it as an output video signal. A signal waveform related to the above-described processing is shown in FIG. 29.
An input/output characteristic of the source driver 2601 is shown in FIG. 30. The source driver 2601, in which the output video signal output from the frequency converting section 2701 is input, alternately converts a signal level of the output video signal so as to be a level greater or smaller than a reference potential, in accordance with a polarity control signal output from the driving pulse generating section 2702, and outputs it. When a level of an output signal of the source driver 2601 is greater than the reference potential, a positive voltage is applied to liquid crystal cells. On the other hand, when a level of an output signal of the source driver 2601 is smaller than the reference potential, a negative voltage is applied to the liquid crystal cells. Also, the greater a signal level of the output video signal becomes, the closer a level of the output signal of the source driver 2601 approaches the reference potential (that is, a voltage applied to the liquid crystal cells becomes smaller).
In FIG. 31, gate pulses P1 to P12 respectively select gate lines GL 1 to GL 12 on the liquid crystal panel 2703 during their respective HI periods. Note that “+”, “−” marked in the HI period of the respective gate pulses P1 to P12 indicate a polarity of a signal (that is, a polarity of an applied voltage) written into a pixel on the gate line selected by the gate pulse. During a period T0_0, the gate pulses P5 to P8 becomes HI at the same time, and a non-image signal in positive polarity is concurrently written into pixels on the gate lines GL5 to GL8. During a following period T0_1 through T0_4, the gate pulses P1 to P4 sequentially become HI, and image signals S1 to S4 in positive polarity are sequentially written into pixels on the gate lines GL1 to GL4. During a period T0_5, the gate pulses P9 to P12 become HI at the same time, and a non-image signal in negative polarity is concurrently written into the gate lines GL9 to GL12. During a following period T0_6 through T0_9, the gate pulses P5 to P8 sequentially become HI, and image signals S5 to S8 in negative polarity are sequentially written into pixels on the gate lines GL5 to GL8, respectively. Here, the respective pixels on the gate lines GL5 to GL8 hold the non-image signal after the non-image signal is written thereinto until an image signal is written thereinto, that is, during the time periods T0_1 through T0_5, T0_1 through T0_6, T0_1 through T0_7, T0_1 through T0_8, respectively. As such, all the gate lines on the liquid crystal panel 107 are respectively selected twice during one frame period, and one image signal and one non-image signal are written into each pixel on the respective gate lines during one frame period.
During a period T1_0 in a following frame period, the gate pulses P5 to P8 become HI at the same time, and the non-image signal in negative polarity (polarity opposite to that in the previous frame) is written into pixels on the gate lines GL5 to GL8. During a following period T1_1 trough T1_4, the gate pulses P1 to P4 sequentially become HI, and image signals S′1 to S′4 in negative polarity (polarity opposite to that in the previous frame) are sequentially written into the pixels on the gate lines GL1 to GL4.
As described above, according to the liquid crystal display apparatus shown in FIG. 27, it is possible to alternately write an image signal and a non-image signal into each pixel on the liquid crystal panel 2703 while minimizing increase in a driving frequency (Japanese Patent Application No. 2001-131414).
Now, the anti-back-transition driving performed by the above liquid crystal display apparatus (that is, anti-back-transition driving by which increase in a driving frequency is minimized by concurrently writing a non-image signal into a plurality of gate lines) restricts the number of horizontal scanning periods composing one frame period.
For example, in a scheme typified by the above-described liquid crystal display apparatus, in which a non-image signal is concurrently written into four gate lines, the number of horizontal scanning periods composing one frame period has to be an odd multiple of five at the time of completion of frequency conversion (that is, in an output video signal). In the example of FIG. 31, the number of horizontal scanning periods composing one frame period (period T0_0 through T0_14) in the output video signal is 15 (an odd multiple of five), thereby satisfying the condition. In general terms, this condition is expressed such that, in a scheme in which a non-image signal is concurrently written into L gate lines, the number of horizontal scanning periods composing one frame period has to be (L+1)×(2N+1) at the time of completion of frequency conversion. If this condition is not satisfied, there will appear irregularity of brightness, that is, some lines are relatively bright and some lines are relatively dark, on a display screen of the liquid crystal panel 2703. Hereinafter, a cause thereof will be briefly described.
FIG. 32 shows various signal waveforms in a scheme in which a non-image signal is concurrently written into three gate lines. In this example, the number of horizontal scanning periods composing one frame period in the output video signal is 16, which is not an odd multiple of four (=3+1), whereby the above-described condition is not satisfied. In FIG. 32, a polarity change of a signal written into pixels on each gate line shows that an image signal whose polarity is opposite to a non-image signal is sure to be written into the gate lines GL1 to GL3 immediately before the non-image signal is written thereinto. On the other hand, with respect to the gate lines GL4 to GL12, an image signal having the same polarity of a non-image signal is sure to be written thereinto immediately before the non-image signal is written thereinto. Now, into a liquid crystal cell into which a signal having a given polarity has already been written, if a signal whose polarity is opposite to that of the above-described signal is written thereinto, there arises a problem of inadequate signal writing compared to a case where a signal having the same polarity of the above-described signal is written thereinto. For this reason, in the example of FIG. 32, writing of a non-image signal into pixels on the gate lines GL1 to GL3 is inadequate compared to writing of a non-image signal into pixels on the other gate lines GL4 to GL12, which results in a difference in brightness between a portion corresponding to the gate lines GL1 to GL3 on the liquid crystal panel 107 and a portion corresponding to the gate lines GL4 to GL12. As such, irregularity of brightness is caused if the aforementioned condition is not satisfied.
In order to prevent the above-described irregularity of brightness, the number of horizontal scanning periods has to be adjusted. However, mere increase or decrease of the number of horizontal scanning periods causes a time lag between writing and reading of an image signal into/from the line memory 2802 as shown in FIG. 29, whereby the line memory 2802 for one line may be insufficient for proper transfer of an image signal (that is, the image signal may be lost). In order to reliably avoid the above-described problem, it is necessary to provide a memory such as a frame memory, for example, capable of concurrently storing image signals for two or more lines, which results in increase in cost of the liquid crystal display apparatus.
Therefore, an object of the present invention is to provide a low-cost liquid crystal display device capable of performing anti-back-transition driving by which increase in a driving frequency is minimized and display of a good-quality video by reducing the occurrence of irregularity of brightness is possible.